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output/Infineon/critique_infineon_doctoral.md

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+# Critique: Infineon Technologies — Doctoral Thesis: AI in Digital Functional Verification (HRC1570652)
+
+**Resume File:** `output/Infineon/e2e_infineon_doctoral_resume.tex`
+**Cover Letter File:** `output/Infineon/e2e_infineon_doctoral_cover_letter.tex`
+**Date:** 2026-03-28
+**Pass:** 2 (post-edit re-critique)
+**Score trajectory:** Pass 1: 73.0 → **Pass 2: 78.0**
+
+---
+
+## Changes Since Pass 1
+
+1. **Header tagline:** `Python, C++, Kubernetes` → `Python, GenAI, Kubernetes`
+2. **Summary:** Java replaces C++ in opening; added GenAI at Swisscom sentence; added verification-intent bridge sentence
+3. **Skills ML group:** Added `generative AI / LLMs` (bold) + `custom GPT development`
+4. **Skills languages:** `Java (strong)` promoted to bold; `C++` demoted to non-bold
+5. **Swisscom bullet 4:** Security Champion replaced with GenAI bullet (real experience)
+6. **Swisscom position title:** Added "GenAI-Driven Engineering"
+7. **Vizrt bullet:** C++ un-bolded
+8. **CL P1:** "Python and C++" → "Python, including current work applying generative AI and custom LLM tooling to automate engineering workflows at Swisscom"
+9. **CorrectBench verified:** Real paper (DATE 2025, TUM lead author under Schlichtmann). Description accurate.
+10. **Dresden confirmed:** Role IS at Infineon's Dresden fab. Header "Open to relocation to Dresden" is correct.
+
+---
+
+## Part 1: Domain-Specialist Lens
+
+*Reused from Pass 1 — lens is built once per JD. Updates noted inline where edits changed the assessment.*
+
+### Reviewer Persona
+*(Unchanged — see Pass 1)*
+
+### Company Context
+*(Unchanged — see Pass 1)*
+
+### JD Vocabulary Extraction (top 10 terms — UPDATED match column)
+
+| # | JD Term | Frequency | Meaning at Infineon | Resume Match? |
+|---|---------|-----------|---------------------|---------------|
+| 1 | AI / machine learning | 8x | AI tooling for verification automation | YES (strong) |
+| 2 | Digital functional verification | 5x | Pre-silicon chip design verification | NO (hard gap) |
+| 3 | Python / C++ | 3x | Scripting + ML development | YES — Python strong; C++ present but de-emphasized |
+| 4 | RISC-V | 3x | AURIX MCU architecture | NO (hard gap) |
+| 5 | UVM | 2x | SystemVerilog testbenches | NO (hard gap) |
+| 6 | Formal verification | 2x | Mathematical proof-based verification | NO (hard gap) |
+| 7 | GenAI / agentic AI | 2x | LLM-based automation workflows | **YES — GenAI (header, summary, skills, bullet, CL). Agentic AI still absent.** |
+| 8 | SoC | 2x | System-on-Chip | NO (hard gap) |
+| 9 | EDA tools | 1x | Cadence/Synopsys/Mentor | NO (hard gap) |
+| 10 | Research / scientific writing | 2x | Academic publication capability | PARTIAL (Fraunhofer + intent sentence) |
+
+### Gap Ranking (UPDATED)
+
+- **Fatal:** Digital functional verification, UVM, formal verification — unchanged. Still the core gap, still bridgeable via "apply AI TO verification" framing.
+- **Serious:** RISC-V, SoC, EDA tools — unchanged. ~~GenAI~~ **Resolved** — GenAI now covered with real experience. "Agentic AI" still absent but less critical.
+- **Cosmetic:** Perl, scientific writing — unchanged.
+
+### Methodology Transfer Test (UPDATED — new GenAI achievement)
+
+| Achievement | How Schlichtmann's Group Sees It |
+|---|---|
+| BS-1: ML inference in 24/7 semiconductor fab | *(unchanged)* "Strong operational ML signal — production deployment in our exact environment." |
+| **NEW — SW-GenAI: Custom GPTs for engineering workflows** | **"This person is already applying LLMs to automate engineering tasks — code review, documentation, troubleshooting. That's exactly what we want to do for verification workflows. Direct methodology transfer."** |
+| FC-2: Fraunhofer ARTUS NLP/speech recognition | *(unchanged)* "Research aptitude + safety-critical ML." |
+| BS-4: ELK/Kafka anomaly detection PoC | *(unchanged)* "Modest bridge to bug detection." |
+| GN-1: BDD test methodology introduction | *(unchanged)* "Test methodology introduction = verification methodology bridge." |
+
+**Key improvement:** The GenAI bullet creates the strongest new transfer — the reviewer can now see "this person already automates engineering tasks with LLMs." Transfer 1-2 (BS-1 + GenAI) are now both natural. This was the biggest gap in Pass 1.
+
+### Competitive Landscape (UPDATED)
+
+- **Our advantage (enhanced):** Now includes (5) current, real GenAI/LLM experience applied to engineering workflows — most fresh graduates won't have production GenAI deployment experience.
+- **Their advantage (slightly reduced):** GenAI was previously a gap. Now the gap is narrower — only "agentic AI" and domain-specific (EDA) GenAI application remain as advantages for the obvious-fit candidate.
+
+---
+
+## Part 2: Five-Perspective Read-Through (UPDATED)
+
+### ATS Robot (keyword scan — UPDATED)
+
+| # | JD Keyword | Resume Match | Type | Change |
+|---|-----------|--------------|------|--------|
+| 1 | AI / artificial intelligence | YES | Verbatim | — |
+| 2 | Machine learning / ML | YES | Verbatim | — |
+| 3 | Python | YES (bold, multiple) | Verbatim | — |
+| 4 | C++ | YES (present, not bold) | Verbatim | ↓ de-emphasized |
+| 5 | Digital functional verification | NO | Absent | — |
+| 6 | Formal verification | NO | Absent | — |
+| 7 | UVM | NO | Absent | — |
+| 8 | RISC-V | NO | Absent | — |
+| 9 | SoC | NO | Absent | — |
+| 10 | GenAI / generative AI | **YES (header, summary, skills, bullet)** | Verbatim | **↑ NEW** |
+| 11 | EDA tools | NO | Absent | — |
+| 12 | Semiconductor | YES | Verbatim | — |
+| 13 | Neural networks | YES | Verbatim | — |
+| 14 | Research | YES | Verbatim | — |
+| 15 | Analytical / problem-solving | Implicit | Semantic | — |
+| 16 | Scientific writing | NO | Absent | — |
+| 17 | Bash | YES | Verbatim | — |
+| 18 | Innovation | NO | Absent | — |
+| 19 | Automation | YES | Verbatim | — |
+| 20 | Deep learning | YES | Verbatim | — |
+| — | LLM (supplementary) | **YES (skills, CL)** | Verbatim | **↑ NEW** |
+
+**Match rate:** 13/20 = 65% — MARGINAL (improved from 55%, still below 70% but the remaining gaps are hard domain terms that can't be added)
+
+### Recruiter Glance (10 seconds)
+
+**Verdict: FORWARD**
+
+Now reads: "ML Engineer | Production AI in Semiconductor Manufacturing | Python, GenAI, Kubernetes." The "GenAI" in the tagline is a direct signal for this AI-focused role. Combined with "Staff Data, Analytics & AI Engineer" title at Swisscom and M.Eng. 1.0, this is a clear forward. The hesitation from Pass 1 is reduced.
+
+### HR Screen (30 seconds)
+
+**Verdict: PHONE SCREEN (upgraded from BORDERLINE)**
+
+Summary now includes: "apply generative AI and custom GPTs to automate development and engineering workflows" + "Motivated to bring ML engineering and semiconductor domain knowledge to AI-based verification research." HR can now see: (a) GenAI experience matches JD emphasis, (b) candidate explicitly signals intent for verification research. The verification-intent sentence is the single most impactful change for this reader.
+
+### Hiring Manager Read (2 minutes)
+
+**Verdict: MAYBE (leaning positive, upgraded from neutral MAYBE)**
+
+**Top 3 observations (updated):**
+1. **Positive (strengthened):** BS-1 still impressive + NOW the Swisscom GenAI bullet shows current LLM engineering experience. "Custom GPTs with domain-specific knowledge bases" demonstrates practical GenAI tool-building, not just prompt use.
+2. **Concern (reduced but still present):** Still zero verification domain knowledge. But the GenAI bullet + intent sentence show the candidate understands the role requires applying AI to a new domain and is already doing analogous work.
+3. **Interesting:** The career arc now reads as a deliberate progression: traditional ML (Bosch) → GenAI engineering (Swisscom) → AI for verification (this role). Narrative coherence improved.
+
+**Predicted first interview question:** *(unchanged)* "Walk me through how you'd approach learning UVM and formal verification well enough to build AI tooling for it."
+
+### Technical Reviewer (10 minutes)
+
+**Truthfulness (updated):**
+- All Pass 1 claims still verified
+- NEW: "Applied generative AI and custom GPTs with domain-specific knowledge bases" — **user-confirmed real experience at Swisscom.** Verified.
+- "reducing manual effort in code review, documentation, and data pipeline troubleshooting" — reasonable impact claim for GenAI tooling. No overclaiming.
+
+**Verb discipline (updated):** "Applied" for GenAI bullet — appropriate full-ownership verb for work the user performs. Pass.
+
+**Over-saturation (updated):**
+- "generative AI" / "GenAI" / "LLM" appears across header + summary + skills + bullet + CL = 5 touchpoints. Acceptable for a role that emphasizes GenAI. Not stuffed — each mention is in a different section serving a different purpose.
+
+**Consistency:** CL now mentions GenAI at Swisscom in P1. Resume has the matching bullet. Consistent.
+
+---
+
+## Part 3: Eight-Dimension Scoring (Pass 2)
+
+| Dimension | Pass 1 | Pass 2 | Weight | Weighted | Change Reason |
+|---|---|---|---|---|---|
+| ATS Keywords | 6.0 | **7.0** | 15% | 1.05 | GenAI/LLM coverage: 55%→65% match rate |
+| Summary | 8.0 | **8.5** | 10% | 0.85 | Verification-intent bridge + GenAI sentence + honest Java/C++ framing |
+| Skills Section | 7.5 | **8.0** | 10% | 0.80 | GenAI/LLMs bold, custom GPT development; Java promoted |
+| Bullet Quality | 8.0 | **8.5** | 25% | 2.125 | GenAI bullet replaces irrelevant Security Champion; strongest new JD bridge |
+| Publications | 5.5 | 5.5 | 10% | 0.55 | Unchanged — structural limitation |
+| Narrative Coherence | 8.0 | **8.5** | 15% | 1.275 | ML → GenAI → AI for verification arc now explicit; intent sentence closes the loop |
+| Page Fill & Visual | 8.0 | 8.0 | 5% | 0.40 | Unchanged — all char counts pass, compile not verified |
+| Credibility Signals | 7.0 | **7.5** | 10% | 0.75 | Current GenAI experience adds signal for AI research role |
+| **Total** | **73.0** | | **100%** | **78.0** | **+5.0 pts** |
+
+**Score interpretation:** 78.0 — Strong for a stretch application. Near the theoretical max (~80) for this candidate-JD pairing. The remaining gap is structural (no verification/EDA domain knowledge) and cannot be closed by resume editing alone.
+
+---
+
+## Part 4: Interview Likelihood (Pass 2)
+
+| Reader | Pass 1 | Pass 2 | Key Factor |
+|--------|--------|--------|------------|
+| ATS | 55% | **60%** | 65% keyword match — marginal but improved |
+| Recruiter (10s) | 70% | **75%** | "GenAI" in tagline + "Staff AI Engineer" title |
+| HR (30s) | 55% | **65%** | Verification-intent sentence + GenAI match = clear forward |
+| Hiring Manager (2m) | 45% | **50%** | GenAI bullet creates stronger bridge; still domain gap |
+| Technical (10m) | 40% | **45%** | LLM engineering experience is directly relevant; verification gap remains |
+
+**Ceiling Analysis (updated):**
+
+| Scenario | Score |
+|----------|-------|
+| Current resume (Pass 2) | 78.0 |
+| + Remaining Tier 2 fixes | ~79 |
+| Theoretical max (this candidate + this JD) | ~80 |
+| Hard ceiling (structural gap) | ~82 |
+| What would close the gap | Verification coursework, an LLM-for-code side project on GitHub, or audit of a UVM/formal verification MOOC |
+
+---
+
+## Part 5: Actionable Improvements (Pass 2)
+
+### Tier 1: HIGH IMPACT — None remaining
+
+All Pass 1 Tier 1 fixes have been applied or resolved:
+- ~~Dresden location~~ — confirmed correct (role is at Infineon Dresden fab)
+- ~~GenAI coverage~~ — applied (header, summary, skills, bullet, CL)
+- ~~Verification-intent bridge~~ — applied (summary sentence)
+
+### Tier 2: MEDIUM IMPACT (optional, diminishing returns)
+
+1. **Add "agentic AI" to skills or summary** — +0.3 pt
+   - JD mentions "agentic AI workflows" specifically. Currently only "generative AI / LLMs" is covered. Could add "agentic AI workflows" to the ML skills group. Only do this if the user has experience with agent-based LLM orchestration.
+
+2. **Vizrt position title: remove "C++"** — +0.2 pt
+   - Current: `Python/C++ Backend Engineering & CI/CD Automation`
+   - Proposed: `Python Backend Engineering & CI/CD Automation`
+   - Rationale: User wants to de-emphasize C++. Position titles are highly visible. Minor but consistent.
+
+3. **Consider a 1-line "Research Interests" statement after Education** — +0.3 pt
+   - Something like: "Interested in: AI-assisted verification methodology, LLM-based code generation for hardware description languages, automated test and assertion generation."
+   - Risk: Claims awareness of topics the candidate hasn't worked in. Could backfire if interviewer probes. Only add if user is comfortable defending these topics.
+
+### Tier 3: COSMETIC (skip)
+
+1. *(carried from Pass 1)* "Data Engineering with AWS Nanodegree" date 2026 — confirm completion year.
+2. CL word count now ~365 words (P1 slightly longer after GenAI addition) — acceptable for academic-industry hybrid.
+
+**Verdict:** No Tier 1 fixes remain. Tier 2 items offer marginal improvement (~0.8 pts total). The resume is at or near its ceiling for this candidate-JD pairing. Recommend submitting.
+
+---
+
+## Part 6: Interview Bridge Points
+
+*(Carried from Pass 1 + one new entry)*
+
+| Resume Topic | Target Equivalent | Opening Line |
+|---|---|---|
+| BS-1: ML inference in 24/7 semiconductor fab | AI verification automation in production flow | "At Bosch, we couldn't inspect every wafer manually — I containerized ML inference to automate it. Verification has the same scaling problem: too many testbenches, not enough engineers." |
+| **SW-GenAI: Custom GPTs for engineering workflows** | **LLM-based tooling for verification workflows** | **"At Swisscom, I build custom GPTs with domain-specific knowledge bases to automate code review and documentation. The same approach — feeding domain knowledge into LLMs to automate engineering tasks — maps directly to building AI tools for verification."** |
+| FC-2: Fraunhofer ARTUS NLP/speech recognition | Applied ML research in safety-critical domain | "At Fraunhofer, I contributed to ML research in a safety-critical domain while building production software alongside. That's the exact structure of this industrial doctorate." |
+| M.Eng. thesis: neural networks + PSO + fuzzy logic | Multi-method AI for engineering systems | "My thesis combined three AI methods for fault diagnosis. Verification will need a similar multi-method approach for assertion generation, testbench creation, and coverage analysis." |
+| BS-4: ELK/Kafka anomaly detection PoC | Pattern detection in system behavior | "Anomaly detection in manufacturing infrastructure is conceptually similar to bug detection in verification — finding unexpected patterns in system behavior." |
+| GN-1: BDD test methodology introduction | Verification methodology adoption | "At Generali, I introduced a new test methodology the organization had never used — PoC, demonstrate value, scale. Same playbook for AI verification." |
+| Initiative pattern across all employers | Research initiative, self-directed methodology development | "At every employer, I independently introduced new tools and methods. That self-directed initiative is what a doctoral research project requires." |
+
+---
+
+## Part 7: Cover Letter Critique (Pass 2)
+
+### 6A-6F: All checks PASS *(carried from Pass 1)*
+
+**Updates:**
+- 6A: CL P1 now includes GenAI at Swisscom — strengthens the "current relevance" signal. Still no defensive language. Pass.
+- 6D: CL now covers GenAI/LLM keywords in P1 — supplements resume coverage. 11/10 high-priority terms. Pass.
+- 6E: Word count ~365 — slightly higher but within range for academic-industry hybrid (300-400). Pass.
+- 6F: GenAI claim in CL (P1) now has matching resume bullet (Swisscom). Package cohesion strengthened.
+- CorrectBench reference: **VERIFIED** — real paper (arXiv:2411.08510, accepted at DATE 2025). Lead author Ruidi Qiu at TUM under Schlichtmann. Description in CL is accurate.
+
+### 6G. AI Fingerprint Scan (re-run)
+
+1. [x] No Tier 1 banned words (re-checked both files)
+2. [x] No banned phrases
+3. [x] Em-dashes: only in cert names and date ranges — acceptable
+4. [x] No vague -ing bullet endings ("data processing" and "data pipeline troubleshooting" are concrete nouns)
+5. [x] CL sentence length variety maintained
+6. [x] Paragraph start variation maintained
+7. [x] Triplet structures: 3 instances — borderline but acceptable for technical content
+8. [x] CL opens with specific JD statistic
+9. [x] No metaphorical banned nouns
+10. [x] Active voice throughout
+11. [x] Cert items use `. `
+12. [x] No banned adverbs
+
+**AI Fingerprint: CLEAN**
+
+---
+
+## Part 8: Post-Generation Verification (Pass 2)
+
+### Mechanical Checks
+
+- [x] All bullets within char limits — no OVER violations (3 NEAR MAX, all within 218 limit)
+- [x] Bullet 15 SHORT (188 chars) — cosmetic, acceptable
+- [x] Cert bullets SHORT — expected for 1L items
+- [ ] **Page fill / orphan check: NOT VERIFIED** — pdflatex unavailable. User must recompile and visually verify 2-page fill before submission.
+
+### Content Checks
+
+- [x] ATS keywords: 65% match (improved from 55%) — remaining gaps are hard domain terms
+- [x] Provenance flags correct — GenAI experience confirmed by user
+- [x] No forbidden terms
+- [x] No inflation — verb discipline maintained
+- [x] CL claims all traceable to resume bullets (including new GenAI claim)
+- [x] Email: dennis@thiessen.io — correct
+
+### Structural Checks
+
+- [x] Company names correct throughout
+- [x] .tex files have complete preambles
+- [x] Date format consistent
+- [x] Email correct
+- [ ] **Page count: NOT VERIFIED** — user must recompile
+- [x] Phone: +49 177 282 7302 — correct German number
+- [x] Generali: Hamburg — correct
+- [x] Dresden: confirmed correct for this role
+
+---
+
+*End of critique — Pass 2.*

output/Infineon/e2e_infineon_doctoral_cover_letter.tex

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+\documentclass[11pt,a4paper,roman]{moderncv}
+\usepackage[english]{babel}
+\moderncvstyle{classic}
+\moderncvcolor{green}
+\usepackage[utf8]{inputenc}
+\usepackage[T1]{fontenc}
+\usepackage{lmodern}
+\usepackage{ragged2e}
+\usepackage[scale=0.79]{geometry}
+\usepackage[version=4,arrows=pgf-filled]{mhchem}
+\renewcommand*{\makeletterclosing}{\par\vspace{2ex}\closingname\par}
+
+\name{Dennis}{Thiessen, M.Eng.}
+\address{Bern, Switzerland}
+\phone[mobile]{+49 177 282 7302}
+\email{dennis@thiessen.io}
+
+\begin{document}
+
+\recipient{Infineon Technologies AG}{Recruiting / Research \& Development\\Re: Doctoral Thesis -- AI in Digital Functional Verification\\Job ID: HRC1570652}
+\date{\today}
+\opening{Dear Members of the Hiring Committee,}
+\makelettertitle
+
+\begin{justify}
+When verification accounts for up to 60\% of SoC development time and the industry faces a projected shortage of verification engineers by 2030, the path forward is clear: build AI tooling that multiplies what each engineer can do. Prof.\ Schlichtmann's group at TUM has already demonstrated this direction with CorrectBench, applying LLMs to automatic testbench generation with functional self-correction. I am applying for the doctoral position (HRC1570652) to contribute to this research, bringing seven years of production ML engineering and semiconductor manufacturing experience in Python, including current work applying generative AI and custom LLM tooling to automate engineering workflows at Swisscom.
+
+At Robert Bosch Semiconductor in Dresden, I faced a structurally similar problem. Manual wafer defect inspection could not scale with fab output, so I containerized ML inference with Docker, Kubernetes, and Ansible to automate image-based defect classification across active 300mm production lines. That work taught me what it takes to deploy ML in a 24/7 constrained environment where failures have immediate production consequences. While my semiconductor experience is in manufacturing analytics rather than chip design verification, the adjacent domain knowledge and production ML engineering depth position me to build AI verification tooling grounded in real operational constraints.
+
+My research background at Fraunhofer CML mirrors the structure of this industrial doctorate: I contributed ML and NLP components to ARTUS, a speech recognition research project in a safety-critical domain, while also building production software alongside the research work. My M.Eng.\ thesis at Tongji University, graded 1.0, applied neural networks, particle swarm optimization, and fuzzy logic to remote fault diagnosis. And at each employer I independently introduced new methods: build automation at Fraunhofer, BDD test frameworks at Generali, centralized monitoring at Bosch.
+
+As a German citizen who lived and worked in Dresden for three years at Bosch, relocating from Bern would be a return, not a fresh start. The combination of Infineon's AURIX RISC-V launch and Prof.\ Schlichtmann's EDA research group represents a rare opportunity to develop AI-based verification methodology at the moment it becomes strategically critical. I would welcome the chance to discuss how my ML engineering background can serve this research direction.
+\end{justify}
+
+\vspace{0.3cm}
+{Sincerely,\\
+Dennis Thiessen, M.Eng.\\
+Staff Data, Analytics \& AI Engineer\\
+Swisscom (Schweiz) AG}
+
+\end{document}

output/Infineon/e2e_infineon_doctoral_resume.tex

@@ -0,0 +1,161 @@
+\documentclass{resume}
+\usepackage{hyperref}
+\usepackage{enumitem}
+\usepackage{fontawesome}
+\usepackage{tikz}
+\usepackage{graphicx}
+\hypersetup{
+    colorlinks = true,
+    linkcolor = [rgb]{0.9,0.4,0.4},
+    anchorcolor = [rgb]{0.9,0.4,0.4},
+    citecolor = [rgb]{0.4,0.4,0.4},
+    filecolor = [rgb]{0.4,0.4,0.4},
+    urlcolor = [rgb]{0.0,0.0,0.99},
+}
+\usepackage{xcolor}
+\usepackage[utf8]{inputenc}
+\usepackage[T1]{fontenc}
+\usepackage{lmodern}
+\usepackage[version=4,arrows=pgf-filled]{mhchem}
+\usepackage[includefoot,left=0.5in,top=0.5in,right=0.5in,bottom=0.2in,textwidth=7.5in,textheight=10.8in]{geometry}
+\usepackage{fancyhdr}
+\pagestyle{fancy}
+\fancyhf{}
+\renewcommand{\headrulewidth}{0pt}
+\fancyfoot[R]{\hfill \thepage/\pageref{LastPage}}
+\newcommand{\tab}[1]{\hspace{.2667\textwidth}\rlap{#1}}
+\newcommand{\itab}[1]{\hspace{0em}\rlap{#1}}
+
+%----------------------------------------------------------------------------------------
+%	HEADER
+%----------------------------------------------------------------------------------------
+\name{Dennis Thiessen, M.Eng.}
+\address{\href{https://linkedin.com/in/dennis-thiessen}{LinkedIn}}
+\address{dennis@thiessen.io \\ +49 177 282 7302}
+\address{Bern, Switzerland $\vert$ German citizen $\vert$ Open to relocation to Dresden}
+\address{{ML Engineer $\vert$ Production AI in Semiconductor Manufacturing $\vert$ Python, GenAI, Kubernetes}}
+
+
+\begin{document}
+
+\vspace{-0.15cm}
+
+%----------------------------------------------------------------------------------------
+%	SUMMARY
+%----------------------------------------------------------------------------------------
+\begin{rSection}{Summary}
+ML and data engineer with 7+ years applying \textbf{Python}, \textbf{Java}, and \textbf{production ML deployment} across semiconductor manufacturing, applied research, and telecom. At Bosch Semiconductor, containerized ML inference (Docker, Kubernetes, Ansible) for automated defect classification in a 24/7 300mm fab. Contributed ML and NLP components to Fraunhofer CML's ARTUS speech recognition research. At Swisscom, apply \textbf{generative AI} and custom GPTs to automate development and engineering workflows alongside production data pipelines. M.Eng.\ (thesis grade 1.0) applying neural networks, PSO, and fuzzy logic. Motivated to bring ML engineering and semiconductor domain knowledge to AI-based verification research. German native, fluent English.
+\end{rSection}
+\vspace{-0.15cm}
+
+%----------------------------------------------------------------------------------------
+%	TECHNICAL SKILLS — Format C, 5 groups (4-3-2-2-2 = 13 lines)
+%----------------------------------------------------------------------------------------
+\begin{rSection}{Technical Skills}
+
+\begin{skillgroup}{Machine Learning \& AI}
+\skilldash{\textbf{ML inference deployment}, MLOps, \textbf{generative AI / LLMs}, custom GPT development, automated defect detection}
+\skilldash{\textbf{NLP}, speech recognition, neural networks, fuzzy logic, particle swarm optimization (PSO), pattern recognition}
+\skilldash{PyTorch, Scikit-learn, TensorFlow/Keras (IBM cert), Pandas, NumPy, Matplotlib, Apache Spark ML}
+\skilldash{Computer vision (wafer defect classification), time-series analysis, statistical modeling, quantitative ML}
+\end{skillgroup}
+
+\begin{skillgroup}{Programming Languages \& Tools}
+\skilldash{\textbf{Python} (expert), \textbf{Java} (strong), C++, C\#, JavaScript, SQL (Oracle, Impala, Teradata, Postgres)}
+\skilldash{PySpark, \textbf{Bash}, Flask/FastAPI, Express.js, .NET/Entity Framework, SQLAlchemy}
+\skilldash{Git, pytest, Agile/Scrum, software architecture (iSAQB CPSA certified), technical documentation}
+\end{skillgroup}
+
+\begin{skillgroup}{Cloud \& Container Infrastructure}
+\skilldash{\textbf{Docker}, \textbf{Kubernetes}, Ansible, AWS (S3, Glue, Athena/Iceberg, Redshift, Lambda, Airflow, CloudFormation)}
+\skilldash{GitLab CI/CD, Jenkins, Infrastructure as Code, DevSecOps, build automation, CI/CD quality gates}
+\end{skillgroup}
+
+\begin{skillgroup}{Data Engineering \& Observability}
+\skilldash{Apache Kafka, Hadoop/ImpalaSQL, OracleDB, Teradata DWH, ETL/ELT pipeline design, data modeling}
+\skilldash{ELK Stack (Elasticsearch, Logstash, Kibana), Grafana, Prometheus, Loki, SQL performance tuning}
+\end{skillgroup}
+
+\begin{skillgroup}{Certifications}
+\skilldash{AWS Certified Solutions Architect -- Associate (2024, active), Data Engineering with AWS (Udacity, 2026)}
+\skilldash{IBM AI Engineering Specialization, AI for Trading Nanodegree (Udacity, 2021), iSAQB CPSA-F (2016)}
+\end{skillgroup}
+
+\end{rSection}
+\vspace{-0.15cm}
+
+%----------------------------------------------------------------------------------------
+%	PROFESSIONAL EXPERIENCE
+%----------------------------------------------------------------------------------------
+\begin{rSection}{Professional Experience}
+
+% --- Swisscom (Oct 2023 -- Present) — 4 bullets: SW-3, SW-1, SW-2, SW-5 ---
+\begin{rSubsection}{GenAI-Driven Engineering, Cloud Data Infrastructure \& Pipelines}{\textcolor{black!60}{Oct 2023 -- Present}}{Staff Data, Analytics \& AI Engineer, Swisscom (Schweiz) AG}{Bern, Switzerland}
+\item Deployed and operated \textbf{Python} applications on \textbf{Kubernetes} with GitLab CI/CD, owning the full containerized delivery lifecycle from build and test automation to production rollout in an agile DevOps team.
+\item Migrated legacy ETL pipelines to \textbf{AWS} (S3, Glue, Athena/Iceberg, Redshift, Airflow, CloudFormation), replacing Teradata/Oracle workflows with scalable, serverless cloud-native data processing.
+\item Owned Fulfillment ETL pipelines (Oracle, Kafka to Teradata DWH in \textbf{Python}) as Component Owner, ensuring data availability, SLA compliance, and Data Governance across business-critical production data flows.
+\item Applied \textbf{generative AI} and custom GPTs with domain-specific knowledge bases to automate development and engineering workflows, reducing manual effort in code review, documentation, and data pipeline troubleshooting.
+\end{rSubsection}
+
+% --- Bosch (Feb 2020 -- Dec 2022) — 4 bullets: BS-1, BS-2, BS-4, BS-3 ---
+\begin{rSubsection}{ML Inference Deployment \& Semiconductor Manufacturing Analytics}{\textcolor{black!60}{Feb 2020 -- Dec 2022}}{(Senior) Data \& ML Engineer, Robert Bosch Semiconductor Manufacturing}{Dresden, Germany}
+\item Containerized \textbf{ML inference} (\textbf{Docker}, \textbf{Kubernetes}, Ansible) for a 24/7 semiconductor fab, automating image-based defect classification and replacing manual wafer inspection across active 300mm production lines.
+\item Built data services in \textbf{Python}, Java, and C\# over OracleDB and Hadoop/ImpalaSQL, supplying semiconductor analysis teams with on-demand access to defect management and process optimization data.
+\item Delivered anomaly detection PoC using ELK Stack and Kafka (\textbf{Docker}) with Grafana/Prometheus/Loki monitoring, validating centralized alerting for 24/7 semiconductor manufacturing infrastructure.
+\item Held Application Owner responsibility for semiconductor analytics platforms and data pipelines, defining SLOs, delivering training, and managing vendor and stakeholder relationships across the fab.
+\end{rSubsection}
+
+% --- Fraunhofer (Sep 2018 -- Oct 2019) — 3 bullets: FC-2, FC-1, FC-3 ---
+\begin{rSubsection}{Applied ML/NLP Research \& Software Engineering}{\textcolor{black!60}{Sep 2018 -- Oct 2019}}{Research Software Engineer, Fraunhofer-Center for Maritime Logistics CML}{Hamburg, Germany}
+\item Contributed \textbf{ML and NLP} components to ARTUS, a Fraunhofer research project for automatic sea rescue speech transcription, applying speech recognition and machine learning in a safety-critical domain.
+\item Set up Jenkins CI/CD pipeline with quality gates independently, introducing build automation to the research team; developed SCEDAS crew scheduling software (C\#, .NET, MS SQL Server, Entity Framework).
+\item Built microservices (Express.js, \textbf{Docker}, SQLite) for MISSION, a Fraunhofer research platform for maritime data exchange between logistics stakeholders including ports, operators, and research partners.
+\end{rSubsection}
+
+% --- Vizrt (Jul 2017 -- May 2018) — 2 bullets: VZ-1, VZ-2 ---
+\begin{rSubsection}{Python/C++ Backend Engineering \& CI/CD Automation}{\textcolor{black!60}{Jul 2017 -- May 2018}}{DevOps Engineer, Vizrt}{Bergen, Norway}
+\item Engineered distributed video transcoding backend components in \textbf{Python} and C++ for Vizrt's broadcast platform, contributing to the core A/V processing pipeline used by CNN, BBC, and Al Jazeera.
+\item Built automated integration and unit test suite for A/V streaming (\textbf{Python}) and integrated quality gates into the CI/CD pipeline, shortening feedback loops and improving release-over-release reliability.
+\end{rSubsection}
+
+% --- Generali (May 2015 -- Jun 2017) — 2 bullets: GN-1, GN-3 ---
+\begin{rSubsection}{Test Automation \& BDD Technical Ownership}{\textcolor{black!60}{May 2015 -- Jun 2017}}{IT Consultant, Generali Deutschland Informatik Services}{Hamburg, Germany}
+\item Introduced BDD test automation to Generali (Serenity-BDD, Selenium, JBehave), running the initial PoC and taking technical ownership; trained project teams and presented the methodology across the Java Community.
+\item Developed Java/J2EE application features for the PIA-Postkorb workflow portal; migrated WebServices to XLDeploy and contributed to an Apache Camel / Spring Boot dispatcher integration PoC.
+\end{rSubsection}
+
+
+\end{rSection}
+\vspace{-0.15cm}
+
+%----------------------------------------------------------------------------------------
+%	EDUCATION — FIXED
+%----------------------------------------------------------------------------------------
+\begin{rSection}{Education}
+{M.Eng.\ Computer Aided Engineering (Software Design \& Engineering)} \hfill {\textcolor{black!60}{Oct 2010 -- Jul 2013}}\\
+{Universität der Bundeswehr München}; thesis at Tongji University, Shanghai \hfill Thesis Grade: \textbf{1.0}\\
+{\small Thesis: \textit{Development of a Web-Based Remote Fault Diagnosis System} (Neural Networks, PSO, Fuzzy Logic)}
+
+{B.Eng.\ Information and Telecommunication Technologies} \hfill {\textcolor{black!60}{Oct 2007 -- Sep 2010}}\\
+{Universität der Bundeswehr München}, Munich, Germany
+\end{rSection}
+\vspace{-0.15cm}
+
+%----------------------------------------------------------------------------------------
+%	CERTIFICATIONS & AWARDS
+%----------------------------------------------------------------------------------------
+\begin{rSection2}{Certifications \& Awards}
+\item \textbf{IBM AI Engineering Specialization}, Coursera. Deep learning, TensorFlow, Keras, Apache Spark ML.
+\item \textbf{AI for Trading Nanodegree}, Udacity / WorldQuant (2021). Quantitative ML, time-series analysis.
+\item \textbf{AWS Certified Solutions Architect -- Associate}, Amazon Web Services (2024, active until Sep 2027).
+\item \textbf{Data Engineering with AWS Nanodegree}, Udacity (2026). AWS data pipeline architecture.
+\item \textbf{iSAQB CPSA -- Foundation Level}, iSAQB (2016). Certified Professional for Software Architecture.
+\item \textbf{ITIL Foundation Certificate in IT Service Management}, PEOPLECERT / AXELOS (2016).
+\end{rSection2}
+
+\begin{center}
+\vspace{0.1cm}
+\textit{Languages: German (native), English (fluent)}
+\end{center}
+
+\end{document}

output/Infineon/infineon_ai_doctoral.txt.txt

@@ -0,0 +1,68 @@
+Job Id
+HRC1570652
+Jobfamilie
+Research & Development
+Beschäftigungsart
+Vollzeit
+Vertragsdauer
+Befristet
+Arbeitsplatztyp
+Hybrid
+Einsteigen als
+PhD Student
+#WeAreIn to create tiny chips and big careers. Curiosity drives progress. Will you drive it with us? As a PhD student at Infineon, you’ll collaborate with passionate minds, shape innovations that power tomorrow’s world, and build a career where your expertise truly makes a difference. Are you in?
+
+Your Role
+
+As part of an industrial doctorate at Infineon, you will pursue a doctoral degree at a university while gaining professional experience at the same time - an ideal way to start your career. You will advance your research with us and benefit from our broad network of doctoral candidates as well as the expertise of a university. Mentorship is provided by both university professors and dedicated Infineon employees. The research will be carried out in cooperation with the Technical University of Munich under the supervision of Prof. Dr.-Ing. Ulf Schlichtmann.
+By 2030, a significant shortage of skilled design and verification engineers is expected. This shortage is further intensified by the increasing complexity of system-on-chips (SoCs), especially those based on RISC-V, which are rapidly gaining adoption due to their open-source nature and flexibility. As complexity rises, verification effort grows proportionally and can account for up to 60% of overall product development time. To reduce time-to-market while maintaining high quality and reliability, innovative solutions are needed to streamline verification processes.
+Artificial intelligence (AI), particularly generative AI (GenAI), has recently emerged as a promising driver of productivity improvements. In both academia and industry, developments such as agentic AI workflows have demonstrated the potential of AI to automate and enhance engineering processes. In the field of digital functional verification, AI has the potential to transform areas such as assertion generation, testbench generation, coverage closure, and bug detection.
+The scope of this doctoral thesis is to develop an AI-based methodology aimed at increasing the productivity of verification engineers, specifically in pre-silicon verification tasks. These include formal verification, Universal Verification Methodology (UVM), and related techniques. By integrating AI-driven approaches into these workflows, the research aims to reduce verification effort, improve process efficiency, and help address the skills gap in this domain.
+
+Key responsibilities in your new role
+
+    Literature research: On existing solutions and state-of-the-art AI-based techniques
+    Focus on the future: Development of an AI-based methodology for digital functional verification
+    Holistic overview: Automation of the AI-based workflow for company-wide adoption
+    Expand your horizons: Application of the methodology on digital designs such as RISC-V processors
+    Data is everything: Documentation and analysis of obtained results
+
+What you will gain
+
+    Deep expertise in design verification
+    Strong practical skills in applying AI to engineering problems
+
+
+
+Your Profile
+
+Qualifications and skills to help you succeed
+
+    Education: You are eligible for full-time PhD studies and hold a master’s degree in Electrical Engineering, Computer Science, or a similar field with excellent results
+    Experience: In the field of digital design and verification methodologies
+    Mandatory skills: Strong analytical and problem-solving skills, as well as excellent programming skills (preferably in Python and C++) with knowledge in AI/ML techniques
+    Preferable skills:
+        Experience with commercial EDA tools for formal verification and simulation
+        Experience with AI/ML applications in design verification or a similar field
+        Familiarity with scripting languages such as Bash and Perl
+
+    Motivation: You are enthusiastic about innovation, research, and scientific writing
+    Way of working: You question the status quo and like to break new ground
+    Language skills: Good written and spoken skills in English; German would be a plus
+
+
+
+
+
+Contact:
+    Rahel Tews
+
+#WeAreIn for driving decarbonization and digitalization.
+As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.
+Are you in?
+
+We are on a journey to create the best Infineon for everyone.
+This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.
+We look forward to receiving your resume, even if you do not entirely meet all the requirements of the job posting.
+Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process.
+Click here for more information about Diversity & Inclusion at Infineon.

output/Infineon/resume.cls

@@ -0,0 +1,199 @@
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+% Medium Length Professional CV - RESUME CLASS FILE
+%
+% This template has been downloaded from:
+% http://www.LaTeXTemplates.com
+%
+% This class file defines the structure and design of the template. 
+%
+% Original header:
+% Copyright (C) 2010 by Trey Hunner
+%
+% Copying and distribution of this file, with or without modification,
+% are permitted in any medium without royalty provided the copyright
+% notice and this notice are preserved. This file is offered as-is,
+% without any warranty.
+%
+% Created by Trey Hunner and modified by www.LaTeXTemplates.com
+%
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
+\ProvidesClass{resume}[2018/09/25 v1.0 Resume class]  
+
+\LoadClass[10pt, a4paper]{article} % Font size and paper type
+\usepackage{lastpage}
+\usepackage[parfill]{parskip} % Remove paragraph indentation
+\usepackage{array} % Required for boldface (\bf and \bfseries) tabular columns
+\usepackage{ifthen} % Required for ifthenelse statements
+\usepackage{enumitem}
+ \pagestyle{empty} % Suppress page numbers
+
+%----------------------------------------------------------------------------------------
+%	HEADINGS COMMANDS: Commands for printing name and address
+%----------------------------------------------------------------------------------------
+
+\def \name#1{\def\@name{#1}} % Defines the \name command to set name
+\def \@name {} % Sets \@name to empty by default
+
+\def \addressSep {$|$} % Set default address separator to a diamond
+
+% One, two or three address lines can be specified 
+\let \@addressone \relax
+\let \@addresstwo \relax
+\let \@addressthree \relax
+\let \@addressfour \relax
+
+% \address command can be used to set the first, second, and third address (last 2 optional)
+\def \address #1{
+  \@ifundefined{@addresstwo}{
+    \def \@addresstwo {#1}
+  }{
+  \@ifundefined{@addressthree}{
+  \def \@addressthree {#1}
+  }{
+  \@ifundefined{@addressfour}{
+  \def \@addressfour {#1}
+  } {\def \@addressone {#1}
+  }
+     
+  }
+  }
+}
+
+% \printaddress is used to style an address line (given as input)
+\def \printaddress #1{
+  \begingroup
+    \def \\ {\addressSep\ }
+             {#1}
+%    \centerline{#1}
+  \endgroup
+  \par
+ % \addressskip
+}
+
+% \printname is used to print the name as a page header
+\def \printname {
+  \begingroup
+  % \MakeUppercase
+  {\namesize\bf \@name} \hfil
+%    \hfil{\MakeUppercase{\namesize\bf \@name}}\hfil
+    \nameskip\break
+  \endgroup
+}
+
+%----------------------------------------------------------------------------------------
+%	PRINT THE HEADING LINES
+%----------------------------------------------------------------------------------------
+
+\let\ori@document=\document
+\renewcommand{\document}{
+  \ori@document  % Begin document
+  % \begin{center}
+  \printname % Print the name specified with \name
+  \@ifundefined{@addressone}{}{ % Print the first address if specified
+    \printaddress{\@addressone}}
+  \@ifundefined{@addresstwo}{}{ % Print the second address if specified
+    \printaddress{\@addresstwo}}
+     \@ifundefined{@addressthree}{}{ % Print the third address if specified
+    \printaddress{\@addressthree}}
+     \@ifundefined{@addressfour}{}{ % Print the third address if specified
+    \printaddress{\@addressfour}}
+    
+    % \end{center}
+}
+
+%----------------------------------------------------------------------------------------
+%	SECTION FORMATTING
+%----------------------------------------------------------------------------------------
+
+% Defines the rSection environment for the large sections within the CV
+\newenvironment{rSection}[1]{ % 1 input argument - section name
+   \sectionskip
+   {\bf #1}
+%   \MakeUppercase{\bf #1} % Section title
+   \sectionlineskip
+  \hrule % Horizontal line
+  \begin{list}{}{ % List for each individual item in the section
+    \setlength{\leftmargin}{0.50em} % Margin within the section
+  }
+  \item[]
+}{
+  \end{list}
+}
+
+\newenvironment{rSection2}[1]{ % 1 input argument - section name
+  \sectionskip
+  {\bf #1} % Section title
+  \sectionlineskip
+  \hrule % Horizontal line
+  \medskip
+  \begin{list}{$\bullet$}{\setlength{\leftmargin}{1.5em}}
+   \itemsep -0.3em \vspace{-0.5em} % Compress items in list together for aesthetics
+}{
+  \end{list}
+ \vspace{0.5em}
+}
+
+\newenvironment{rSection3}[1]{ % 1 input argument - section name
+  \sectionskip
+  {\bf #1} % Section title
+  \sectionlineskip
+  \hrule % Horizontal line
+  \medskip
+  \begin{enumerate}[]{\setlength{\leftmargin}{1.5em}}
+   \itemsep -0.3em \vspace{-0.5em} % Compress items in list together for aesthetics
+}{
+  \end{enumerate}
+ \vspace{0.5em}
+}
+%----------------------------------------------------------------------------------------
+%	WORK EXPERIENCE FORMATTING
+%----------------------------------------------------------------------------------------
+
+\newenvironment{rSubsection}[4]{ % 4 input arguments - company name, year(s) employed, job title and location
+ {\bf #1} \hfill {#2} % Bold company name and date on the right
+ \ifthenelse{\equal{#3}{}}{}{ % If the third argument is not specified, don't print the job title and location line
+  \\
+  {\em #3} \quad {\em #4} % Italic job title and location
+  }\smallskip
+  \begin{list}{$\cdot$}{\leftmargin=1.5em} % \cdot used for bullets, no indentation
+   \itemsep -0.2em \vspace{-0.2em} % Compress items in list together for aesthetics
+  }{
+  \end{list}
+  \vspace{0.2 em} % Some space after the list of bullet points
+}
+
+
+
+%----------------------------------------------------------------------------------------
+%	FORMAT C SKILLS COMMANDS
+%----------------------------------------------------------------------------------------
+
+% Skills group environment: \begin{skillgroup}{Group Name} ... \end{skillgroup}
+% Renders bold header + indented dash sub-items. Each \skilldash = exactly 1 rendered line.
+\newenvironment{skillgroup}[1]{%
+  \textbf{#1}\par\nopagebreak%
+  \vspace{-\parskip}%
+  \begin{list}{--}{\leftmargin=0.8em \labelsep=0.3em \itemsep=0pt \topsep=0.1em \parsep=0pt \partopsep=0pt}%
+}{%
+  \end{list}%
+  \vspace{-\parskip}\vspace{0.45em}%
+}
+
+% Single dash sub-item within a skillgroup. Content must fit 1 rendered line.
+% Char limit: 119 - (0.5 x bold_char_count) at 10pt
+\newcommand{\skilldash}[1]{\item #1}
+
+%----------------------------------------------------------------------------------------
+%	EXPERIENCE SUB-THEME COMMAND
+%----------------------------------------------------------------------------------------
+
+% Sub-theme underline header within rSubsection
+\newcommand{\subtheme}[1]{\item[] \underline{#1}}
+
+% The below commands define the whitespace after certain things in the document - they can be \smallskip, \medskip or \bigskip
+\def\namesize{\huge} % Size of the name at the top of the document
+\def\addressskip{\smallskip} % The space between the two address (or phone/email) lines
+\def\sectionlineskip{\medskip} % The space above the horizontal line for each section 
+\def\nameskip{\medskip} % The space after your name at the top
+\def\sectionskip{\medskip} % The space after the heading section

output/Infineon/session_infineon_doctoral.md

@@ -0,0 +1,196 @@
+# Session: Infineon Technologies — Doctoral Thesis: AI in Digital Functional Verification
+
+## JD Info
+- **File:** JDs/infineon_ai_doctoral.txt.txt
+- **Role:** PhD Student / Doctoral Thesis (Industrial Doctorate)
+- **Company:** Infineon Technologies AG (Munich/Neubiberg, Germany — global semiconductor leader, power systems & IoT)
+- **Partner university:** Technical University of Munich (TUM), Chair of Electronic Design Automation, Prof. Dr.-Ing. Ulf Schlichtmann
+- **Job ID:** HRC1570652
+- **Bundle:** ML/AI Engineer (primary) + Semiconductor domain overlays from significance_bosch.md
+- **Format:** 2-page resume (resume.cls) + 1-page cover letter
+- **Note on bundle:** bundle_semiconductor.md not yet built. Use bundle_ml_ai_engineer.md + explicit semiconductor framing. Build semiconductor bundle after this session.
+
+## JD Analysis
+
+### Requirements
+
+| # | Requirement | Match | Evidence |
+|---|-------------|-------|----------|
+| 1 | Master's degree CS / EE / similar | **Direct** | M.Eng. Computer Aided Engineering (Software Design & Engineering focus), UniBw München |
+| 2 | Eligible for full-time PhD | **Direct** | Holds M.Eng. — eligible. Thesis grade 1.0 (top grade) signals academic capability |
+| 3 | Excellent academic results | **Direct** | M.Eng. thesis grade 1.0; overall 1.6 (gut) |
+| 4 | Python programming (strong) | **Direct** | Expert — all positions, Swisscom/Bosch/Fraunhofer/Vizrt |
+| 5 | C++ programming (strong) | **Direct** | Proficient — Vizrt backend transcoding, Generali |
+| 6 | AI/ML techniques knowledge | **Direct** | Bosch ML deployment (production), Udacity AI for Trading, IBM AI Engineering Spec. |
+| 7 | Analytical and problem-solving skills | **Direct** | Confirmed by 4 employer references; thesis (PSO, Neural Networks, Fuzzy Logic) |
+| 8 | English (good written/spoken) | **Direct** | Fluent — Vizrt (Norwegian company, English working language) |
+| 9 | German (plus) | **Direct** | Native speaker |
+| 10 | Experience in digital design & verification | **GAP** | Dennis has NO hardware design/EDA experience. His semiconductor work is manufacturing DATA, not chip design |
+| 11 | EDA tools (formal verification, simulation) | **GAP** | No Cadence, Synopsys, Mentor, or similar EDA tool experience |
+| 12 | UVM (Universal Verification Methodology) | **GAP** | No SystemVerilog/UVM testbench experience |
+| 13 | RISC-V knowledge | **GAP** | No RISC-V architecture background |
+| 14 | AI/ML in design verification | **Bridge (MED)** | Bosch ML in semiconductor domain (manufacturing side) → closest bridge; Fraunhofer NLP research |
+| 15 | Agentic AI / GenAI workflows | **Bridge (LOW-MED)** | General ML/AI experience; no specific GenAI/LLM-for-EDA work |
+| 16 | Bash scripting | **Bridge (MED)** | Likely from CI/CD work (Jenkins, GitLab) but not explicitly confirmed in extractions |
+| 17 | Perl | **GAP** | Not evidenced |
+| 18 | Research motivation / scientific writing | **Bridge (MED)** | Fraunhofer CML research role (ARTUS, MISSION, grant proposal); M.Eng. thesis |
+| 19 | Innovation / breaking new ground | **Direct** | Multiple Zeugnisse confirm: introduced CI/CD (Fraunhofer), introduced BDD (Generali), ELK PoC (Bosch) |
+
+### ATS Keywords
+
+- **AI/ML:** AI, machine learning, generative AI, GenAI, LLM, neural networks, deep learning, Python, C++
+- **Domain:** digital functional verification, formal verification, UVM, SystemVerilog, RISC-V, SoC, EDA, simulation, testbench, coverage closure, assertion generation, bug detection
+- **Methods:** agentic AI, AI workflow automation, pre-silicon verification, verification methodology
+- **Tools:** EDA tools (formal verification, simulation), UVM framework
+- **Soft skills:** analytical thinking, research, scientific writing, innovation, problem-solving
+
+### Gap Assessment
+
+- **Direct (9):** M.Eng. CS, PhD eligibility, excellent grades, Python, C++, AI/ML knowledge, analytical skills, English, German
+- **Bridge (4):** AI for semiconductor domain (MED), agentic/GenAI (LOW-MED), research background/Fraunhofer (MED), Bash (MED)
+- **Gap (5 — SIGNIFICANT):** Digital design/verification, EDA tools, UVM/SystemVerilog, RISC-V, Perl
+
+**⚠️ CRITICAL GAP WARNING:** The core research domain — hardware digital functional verification (UVM, formal verification, EDA tools) — is not in Dennis's background. His semiconductor experience is manufacturing analytics/data engineering, not chip design or verification. This is a fundamental domain mismatch. The framing strategy must acknowledge this and build the strongest possible bridge through AI/ML angle + semiconductor domain familiarity. User should be aware this is a stretch application.
+
+---
+
+## Company Context
+
+- **Mission:** Infineon is a global top-10 semiconductor company specializing in power systems, automotive (AURIX MCU family), IoT, and security chips. Revenue ~€15B, ~58,000 employees.
+- **RISC-V strategy:** Infineon is actively launching AURIX RISC-V automotive MCU family — a strategic bet. Verification tooling for RISC-V designs is a genuine bottleneck identified in the JD. The role is solving a real company-wide problem.
+- **AI for EDA:** Prof. Schlichtmann's TUM EDA Chair is actively publishing on LLMs for EDA (design, verification, testing). This is a credible, active research group — not a theoretical JD.
+- **This role:** Industry doctoral student splits time between TUM research (with Schlichtmann group) and Infineon's verification engineering teams. Outcome = PhD thesis + company-wide AI verification methodology.
+- **Culture signals:** "Curiosity drives progress", "question the status quo", "break new ground" — research-forward, innovation-oriented. Not a standard engineering role.
+- **"Why them" angle:** Infineon is one of the few companies globally with both the RISC-V manufacturing commitment AND the TUM academic partnership to develop AI verification at scale. The timing (AURIX RISC-V launch + skills shortage by 2030) makes this research genuinely impactful.
+- **Recruiter:** Rahel Tews
+
+---
+
+## Framing Strategy
+
+**Lead narrative:** "AI/ML engineer with semiconductor manufacturing domain knowledge, strong Python/C++ skills, and research background — applying ML engineering expertise to the emerging field of AI-assisted chip verification. Not a verification engineer by training, but an ML engineer who understands the semiconductor domain and has the technical foundation to build AI tooling for it."
+
+**Reframing map:**
+- ML inference deployment (Bosch) → "production ML engineering in semiconductor manufacturing environment"
+- Semiconductor data domain (defect management) → "semiconductor domain knowledge — manufacturing analytics side"
+- Fraunhofer ARTUS NLP → "applied ML/NLP research in safety-critical domain"
+- M.Eng. thesis (Neural Networks, PSO, Fuzzy) → "AI/ML applied to engineering systems — academic foundation"
+- Test automation (Generali, Vizrt) → "verification mindset — building systematic test coverage" (bridge to verification)
+- CI/CD quality gates (Vizrt, Fraunhofer) → "automated quality workflows" (bridge to verification automation)
+
+**Emphasize:**
+- AI/ML depth + Python/C++ (exact language match)
+- Semiconductor domain knowledge (even if manufacturing side)
+- M.Eng. academic credentials + thesis grade (1.0 — top)
+- Fraunhofer research background (ML research context)
+- Initiative signals (introduced CI/CD, BDD, ELK PoC independently)
+- German native (strong plus for Munich-based role)
+
+**Downplay:**
+- Pure data engineering / ETL pipeline work (not relevant)
+- Kafka, Teradata, SAP BODS, AWS Glue (infrastructure — not relevant for research role)
+- Test automation heritage from Generali/Capgemini (keep conceptual bridge only)
+- Bosch Application Owner / SLO / stakeholder management (operational role — not research)
+
+**CL hooks:**
+- Prof. Schlichtmann's group publishes on LLMs for EDA — can reference this research direction
+- AURIX RISC-V is a concrete product line — tie research to real Infineon designs
+- "Verification can account for up to 60% of development time" → the JD's own statistic is a powerful hook
+- Fraunhofer CML experience: research + industry hybrid (same structure as this doctorate)
+
+**Honest gap acknowledgment approach:** Do NOT pretend to have EDA experience. Instead: acknowledge the domain shift, frame it as deliberate pivot, and argue that an ML engineer who understands semiconductor manufacturing is better positioned than a pure software engineer who has never seen a fab.
+
+---
+
+## Critique Context
+
+- **Reviewer persona:** Likely two reviewers: (1) HR/recruiter (Rahel Tews) — screens for PhD eligibility, language, basic technical fit; (2) Prof. Schlichtmann or Infineon research engineer — evaluates AI/ML depth, research aptitude, semiconductor domain awareness
+- **Competitive landscape:** "Obvious fit" candidates have CS/EE master's + some verification coursework + ML project experience. Dennis lacks the verification coursework but has stronger industry ML deployment experience and unique semiconductor manufacturing context. He needs to out-compete on the AI/ML engineering depth axis.
+- **Domain vocabulary to use:** "digital functional verification", "pre-silicon verification", "formal verification", "UVM", "assertion generation", "testbench", "SoC", "RISC-V" — use in CL even if not in resume. Shows awareness of the domain.
+
+---
+
+## Cover Letter Plan
+
+- **Institution type:** Industry-academic hybrid (industrial doctorate)
+- **Paragraph count:** 4 paragraphs, ~280 words
+- **P1 hook:** Open with the 60% verification time statistic from the JD + position self as ML engineer who wants to solve this with AI tooling. Reference Schlichtmann group's LLM-for-EDA research direction.
+- **P2 evidence:** AI/ML credentials (Bosch production ML, IBM AI Engineering, Python/C++) + semiconductor manufacturing domain familiarity — argue this gives a unique angle vs. pure software ML candidates
+- **P3 evidence:** Research background (Fraunhofer CML — industrial research, same structure as this doctorate) + M.Eng. thesis (AI/ML methods: neural networks, PSO, fuzzy) + initiative signal (independently introduced CI/CD/BDD/ELK at multiple employers)
+- **P4 close:** German native, Munich-familiar, motivated by the specific research problem (AI for verification gap). Express genuine interest in Schlichtmann group's research direction.
+- **Domain pivot sentence:** "While my primary experience has been in applying ML to semiconductor manufacturing analytics rather than chip design verification, the adjacent domain knowledge and production ML engineering depth position me to contribute meaningfully to an AI-first verification methodology."
+- **Jargon level:** Technical (for research audience) but honest about domain gaps
+- **"Why them" hook:** Infineon's AURIX RISC-V launch + TUM EDA Chair partnership = unique opportunity to develop AI verification at the exact moment it becomes strategically critical
+
+---
+
+## Bullet Plan
+
+### Key Framing Insight (from user — confirmed Phase 1)
+**Automation-necessity parallel — use in BS-1 and CL:**
+> "At Bosch, we couldn't hire enough engineers to classify/detect/root-cause all defects at scale → automated with ML/image recognition."
+> Infineon's problem statement is structurally identical: verification consumes 60% of dev time, engineer shortage projected by 2030 → automate with AI.
+> This is the strongest bridge argument in the application. BS-1 leads with this problem-driven framing.
+
+### Confirmed Bullet Allocations
+
+| Position | IDs | Count | Variant |
+|----------|-----|-------|---------|
+| Swisscom (Oct 2023–Present) | SW-3, SW-1, SW-2 | 3 | 2L each |
+| Bosch (Feb 2020–Dec 2022) | BS-1, BS-2, BS-4, BS-3 | 4 | 2L each |
+| Fraunhofer (Sep 2018–Oct 2019) | FC-2, FC-1 | 2 | 2L each |
+| Vizrt (Jul 2017–May 2018) | VZ-1+VZ-2 combined | 1 | 2L |
+| Generali | — | 0 | dropped |
+| **Total** | | **10** | all 2L |
+
+**Excluded:** SW-5 (user preference → SW-2), SW-4, BS-3 ordering (placed 4th per narrative), FC-3, FC-4, GN-1 (dropped to give Bosch 4 bullets)
+
+### Position Title Adjustments
+- Bosch: "Data & ML Engineer" (ML framing per experience file flexibility)
+- Vizrt: "DevOps Engineer" (keep standard)
+
+### JD Coverage Map
+- Python: SW-3, BS-2, FC-2, VZ combined ✓
+- C++: VZ-1+VZ-2 combined (explicit call-out) ✓
+- ML/AI: BS-1 (flagship), BS-4, FC-2, SW-3 ✓
+- Semiconductor domain: BS-1, BS-2 ✓
+- Research background: FC-2, FC-1 (Fraunhofer industrial research) ✓
+- Initiative / independent contributor: FC-1 CI/CD, BS-4 PoC ✓
+- Automation-necessity bridge: BS-1 problem framing ✓
+
+---
+
+## Output Files
+- Resume: `output/Infineon/e2e_infineon_doctoral_resume.tex`
+- Cover Letter: `output/Infineon/e2e_infineon_doctoral_cover_letter.tex`
+- Critique: `output/Infineon/critique_infineon_doctoral.md`
+
+---
+
+## Status
+- Phase 0: DONE
+- Phase 1: DONE (17 bullets confirmed — expanded from 10 to fill 2 pages)
+- Phase 2 Resume: DONE (17 bullets across 6 positions, all char counts pass, compiled 2 pages with MiKTeX)
+- Cover Letter: DONE (1 page, ~349 words, 4 paragraphs, all hooks verified)
+- Critique: CURRENT (Pass 2: 78.0/100, up from Pass 1: 73.0)
+- Edits Applied: GenAI added (summary, skills, Swisscom bullet, header, CL P1); C++ de-emphasized (Java promoted); verification-intent sentence added to summary; SW-5 Security Champion replaced with GenAI bullet
+- **Next:** Recompile with MiKTeX, visually verify 2-page fill, then submit
+
+## Critique Summary (Pass 2)
+
+**Score:** 78.0/100 (up from 73.0) — near theoretical ceiling for this candidate-JD pairing.
+
+**Key findings:**
+- ATS keyword match: 65% (13/20) — improved from 55%; remaining gaps are hard domain terms
+- Bullet quality: 8.5/10 — GenAI bullet is strongest new JD bridge
+- CL: all checks pass, CorrectBench verified (DATE 2025, TUM lead author), GenAI integrated
+- AI fingerprint: clean
+- No provenance or accuracy violations
+- No Tier 1 fixes remaining
+
+**Interview likelihood:** 50% at HM level — improved from 45%. Depends on competitive field size.
+
+**Remaining Tier 2 (optional, diminishing returns):**
+1. Add "agentic AI" to skills (+0.3) — only if user has agent-based LLM orchestration experience
+2. Remove "C++" from Vizrt position title (+0.2)
+3. Add 1-line "Research Interests" after Education (+0.3) — risky if can't defend in interview