42 lines
3.3 KiB
TeX
42 lines
3.3 KiB
TeX
\documentclass[11pt,a4paper,roman]{moderncv}
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\usepackage[english]{babel}
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\moderncvstyle{classic}
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\moderncvcolor{green}
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\usepackage[utf8]{inputenc}
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\usepackage[T1]{fontenc}
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\usepackage{lmodern}
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\usepackage{ragged2e}
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\usepackage[scale=0.79]{geometry}
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\usepackage[version=4,arrows=pgf-filled]{mhchem}
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\renewcommand*{\makeletterclosing}{\par\vspace{2ex}\closingname\par}
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\name{Dennis}{Thiessen, M.Eng.}
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\address{Bern, Switzerland}
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\phone[mobile]{+49 177 282 7302}
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\email{dennis@thiessen.io}
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\begin{document}
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\recipient{Infineon Technologies AG}{Recruiting / Research \& Development\\Re: Doctoral Thesis -- AI in Digital Functional Verification\\Job ID: HRC1570652}
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\date{\today}
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\opening{Dear Members of the Hiring Committee,}
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\makelettertitle
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\begin{justify}
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When verification accounts for up to 60\% of SoC development time and the industry faces a projected shortage of verification engineers by 2030, the path forward is clear: build AI tooling that multiplies what each engineer can do. Prof.\ Schlichtmann's group at TUM has already demonstrated this direction with CorrectBench, applying LLMs to automatic testbench generation with functional self-correction. I am applying for the doctoral position (HRC1570652) to contribute to this research, bringing seven years of production ML engineering and semiconductor manufacturing experience in Python, including current work applying generative AI and custom LLM tooling to automate engineering workflows at Swisscom.
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At Robert Bosch Semiconductor in Dresden, I faced a structurally similar problem. Manual wafer defect inspection could not scale with fab output, so I containerized ML inference with Docker, Kubernetes, and Ansible to automate image-based defect classification across active 300mm production lines. That work taught me what it takes to deploy ML in a 24/7 constrained environment where failures have immediate production consequences. While my semiconductor experience is in manufacturing analytics rather than chip design verification, the adjacent domain knowledge and production ML engineering depth position me to build AI verification tooling grounded in real operational constraints.
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My research background at Fraunhofer CML mirrors the structure of this industrial doctorate: I contributed ML and NLP components to ARTUS, a speech recognition research project in a safety-critical domain, while also building production software alongside the research work. My M.Eng.\ thesis at Tongji University, graded 1.0, applied neural networks, particle swarm optimization, and fuzzy logic to remote fault diagnosis. And at each employer I independently introduced new methods: build automation at Fraunhofer, BDD test frameworks at Generali, centralized monitoring at Bosch.
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As a German citizen who lived and worked in Dresden for three years at Bosch, relocating from Bern would be a return, not a fresh start. The combination of Infineon's AURIX RISC-V launch and Prof.\ Schlichtmann's EDA research group represents a rare opportunity to develop AI-based verification methodology at the moment it becomes strategically critical. I would welcome the chance to discuss how my ML engineering background can serve this research direction.
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\end{justify}
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\vspace{0.3cm}
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{Sincerely,\\
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Dennis Thiessen, M.Eng.\\
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Staff Data, Analytics \& AI Engineer\\
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Swisscom (Schweiz) AG}
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\end{document}
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